1. Field of the Invention
The invention relates to a dual power memory, and more particularly to a pre-decoder of a dual power memory
2. Description of the Related Art
Since process technologies have been scaled down, such as deep sub-micron process technologies, the layout area of a system on chip (SOC) has greatly been decreased. However, memory device reliability (e.g. static random access memory (SRAM)) for SOCs with greatly decreased sizes is poor due to low supply voltages, threshold voltage mismatch caused by process variations and so on. For example, a threshold voltage mismatch of a memory device is about 35 mV/sigma for the 65 nm process. Moreover, such threshold voltage mismatch of a memory device is hard to estimate or simulate by a SPICE corner model, such as an SS (slow PMOS, slow NMOS), TT (typical PMOS, typical NMOS), FF (fast PMOS, fast NMOS), SF, or FS model.
In general, a 10 Mbit memory or greater, is common in an SOC. If a memory device of the SOC is operated with low supply voltage, read/write failure occurs due to threshold voltage mismatch among the memory cells. Furthermore, defect density of read/write failure is increased when supply voltage is decreased.
FIG. 1 shows a schematic diagram of an SRAM 110, wherein the SRAM 110 is implemented in an integrated circuit 100. The integrated circuit 100 further comprises a random logic 120 which is powered by a supply voltage VDD. The SRAM 110 comprises a memory array 111 with a plurality of memory cells, a level shifter 112, a word line (WL) decoder 113 for decoding the address signals to obtain the predecode signals, a control unit 114 for controlling the read/write operations, and an input/output (I/O) unit 115 for receiving and transmitting data between the SRAM 110 and the random logic 120. Note that there could be an address, clock, and read/write control signals running between the control unit 114 and the random logic 120. In order to avoid read/write failure for the SRAM 110, the memory array 111 is powered by a supply voltage CVDD which is higher than the supply voltage VDD. The level shifter 112 is disposed between the word line decoder 113 and the memory array 111, which is used to change the voltage levels of signals generated by the word line decoder 113 from the supply voltage VDD level to the supply voltage CVDD level, so as to drive the memory array 111.
FIG. 2 shows a word line driver array 200 with a plurality of dual power rail drivers, wherein the word line driver array 200 is coupled between a word line decoder 202 powered by the supply voltage VDD and a memory array 204 powered by the supply voltage CVDD. The word line decoder 202 provides a pulse signal XPC indicating that one section of the SRAM corresponding to the address signals has been selected. The word line decoder 202 further provides a plurality of predecode signals (ex. predecode[0], predecode[1], predecode[2] etc.) to the word line driver array 200 according to the address signals ADD. Each dual power rail driver of the word line driver array 200 generates a word line signal according to the corresponding predecode signal and the pulse signal XPC. For example, when the pulse signal XPC is asserted, the driver 210 generates a word line signal WL[0] according to the predecode signal predecode[0], the driver 220 generates a word line signal WL[1] according to the predecode signal predecode[1], the driver 230 generates a word line signal WL[2] according to the predecode signal predecode[2] and so on. In the word line driver array 200, each word line driver has a level shifter, such as a level shifter 212 of the driver 210, a level shifter 222 of the driver 220 or a level shifter 232 of the driver 230, wherein each level shifter is disposed in data transmission path. Therefore, layout area and extra gate-delay in the critical timing path are increased, thus slowing access of the memory array.
FIG. 3 shows another word line driver array 300 with a plurality of dual power rail drivers, wherein the word line driver array 300 is coupled between a word line decoder 302 powered by the supply voltage VDD and a memory array 304 powered by the supply voltage CVDD. Compared with the word line driver array 200 of FIG. 2, no level shifter exists in the data transmission path for each word line driver in the word line driver array 300, thereby the layout area of the word line driver array 300 is smaller than that of the word line driver array 200 of FIG. 2. However, a level shifter 306 disposed in the pulse signal transmission path is used to change the voltage levels of a pulse signal XPC generated by the word line decoder 302 from the supply voltage VDD level to the supply voltage CVDD level. Therefore, an extra gate-delay in the critical timing path is increased, thus slowing access of the memory array.
FIG. 4 shows a schematic diagram illustrating a conventional single power rail pre-decoder 400. The pre-decoder 400 can be implemented in the word line decoder 202 of FIG. 2. The pre-decoder 400 comprises an address latch and decoder 410, a clock generator 420, a NAND gate 430 and an inverter 440. The clock generator 420 generates a pulse signal WLP according to a clock CLK, and provides the pulse signal WLP to the address latch and decoder 410 and the NAND gate 430. The address latch and decoder 410 generates a decoded signal PRC according to an address ADD and the pulse signal WLP. The NAND gate 430 generates a signal XPCB according to the decoded signal PRC and the pulse signal WLP. The inverter 440 inverts the signal XPCB to obtain a signal XPC. The signal XPC is a pulse signal indicating that one section of a memory array corresponding to the address ADD has been selected.
FIG. 5 shows a waveform illustrating the ideal timing considerations of a memory array. A setup time T_setup is the minimum amount of time that the address ADD should be held steady before a rising edge of the clock CLK, so that the address ADD is reliably sampled by the clock CLK. An access time T_access is the time that it takes a memory array to deliver the data DO in response to the address ADD. Therefore, according to the setup time T_setup and the access time T_access, a minimum clock period T_clock is given by the following equation:T_clock=T_setup+T_access.
FIG. 6 shows a schematic diagram illustrating a conventional dual power rail pre-decoder 500. The pre-decoder 500 can be implemented in the word line decoder 302 of FIG. 3. Compared with the pre-decoder 400 of FIG. 4, the pre-decoder 500 further comprises a level shifter 510, wherein the level shifter 510 receives the signal XPC powered by the supply voltage VDD to provide a signal XPC_LS which is powered by the supply voltage CVDD. Therefore, an extra gate-delay T_level_shifter is increased for the access time T_access, thereby the clock period T_clock is also increased. The increased clock period T_clock is given by the following equation:
                    T_clock        =                  T_setup          +                      T_access            ⁢            _new                                                  =                  T_setup          +          T_access          +                      T_level            ⁢                          _shifter              .                                          
Therefore, it is desired to insert a level shifter in a critical timing path without affecting the clock period T_clock.